ISP-8A/600 single-chip 8-bit n-channel microprocessor (SC/MP-II)

This document transcribed by Paul Robson (autismuk@aol.com). Some details and illustrations have been omitted (but are available if required). A briefer introduction to this chip is here.

general description

SC/MP (Simple Cost-effective MicroProcessor) is a single-chip 8-bit microprocessor packaged in a standard 40 pin dual-in-line package. N-channel, silicon gate, depletion mode standard process technology ensures high performance, high reliability and high producibility.

SC/MP is intended for use in general-purpose applications where cost per function is a most significant criterion. But cost efficiency is only a part of SC/MP's story. It goes on to include a variety of useful functions that are not even provided by some of the expensive microprocessors, like self-contained timing circuitry, 16-bit (65k) addressing capability, serial or parallel data-transfer capability and common memory / peripheral instructions. The built in features in conjunction with the low initial cost describe what SC/MP real is - a microprocessor specifically designed to provide the simplest and most efficient solution to many application requirements.

customer benefits

SC/MP Pinout
1 NWDS
2 NRDS
3 NENIN
4 NENOUT
5 NBREQ
6 NHOLD
7 NRST
8 CONT
9..16 DB7 .. DB0 (in that order)
17 SENSE A
18 SENSE B
19 FLAG 0
20 GND
21 FLAG 1
22 FLAG 2
23 SOUT
24 SIN
25-36 A0 .. A11
37 XIN
38 XOUT
39 NADS
40 Vcc

applications

ratings & electrical characteristics

not yet available

functional description

SC/MP is a self contained general purpose microprocessor designed for ease of implementation in stand-alone DMA (Direct Memory Access) and multiprocessor applications. Communications between SC/MP and external memory/address devices are effected via a 12-bit dedicated address bus and an 8 bit bidirectional data bus. During the address interval of each input/output cycle, SC/MP employs both busses to provide a 16-bit address output : the 12 least significant address bits are sent out over the 12-bit address bus and the 4 most significant address bits are sent out over the 8 bit data bus along with 4 status bits. Separate strobe outputs from SC/MP (NADS,NWDS,NRDS indicate when valid address information is present on the two busses and when valid input/output memory or peripheral data are present on the 8-bit bus. To further extend flexibility of application serial data input/output ports are also provided so the serial data transfers can be effected under program control. The remaining input/output signals are dedicated to general purpose control and status functions, including initialisation, bus management, microprocessor halt, interrupt request, input/output cycle extension and user-specified hardware / software interface functions. A detailed description of each input/output signal is provided in table 1.

Table 1. Input/Output Signal Description

Signal Mnemonic

Functional Name

Description

NRST

Reset Input

Set high for normal operation. When set low, aborts in process operations. When returned high, internal control circuit zeroes all programmer accessible registers: then , first instruction is fetched from memory location 0001.

CONT

Continue Input

When set high, enables normal execution of program stored in external memory. When set low, SC/MP operation is suspended (after completion of current instruction) without loss of internal status.

NBREQ

Bus Request Input/Output

Associated with SC/MP internal allocation logic for system bus. Can be used as bus request output or bus busy input. Requires external load resistor to Vcc.

NENIN

Enable Input

Associated with SC/MP internal allocation logic for system bus. When set low, SC/MP is granted access to system buses. When set high, places system buses in high impedance (Tristate) mode

NENOUT

Enable Output

Associated with SC/MP internal allocation logic for system bus. Set low when NENIN is low and SC/MP is not using system buses (NBREQ-high). Set high at all other times.

NADS

Address Strobe Output

Active-low strobe. While low, indicates that valid address and status output are present on system buses.

NRDS

Read Strobe Output

Active low strobe. On trailing edge, data are input to SC/MP from 8 bit bidirectional data bus. High impedance output when input/output cycle is not in progress.

NWDS

Write Strobe Output

Active low strobe. While low, indicates that valid output are present on 8 bit bidirectional data bus. High impedance output when input/output cycle not in progress.

NHOLD

Input/Output Cycle Extend Input

When set low prior to trailing edge of NRDS or NWDS strobe stretches strobe to extend input/output cycle - that is, strobe is held low until NHOLD signal is returned high.

SENSE A

Sense / Interrupt Request Input

Serves as interrupt request input when SC/MP internal IE (Interrupt Enable) flag is set. When IE flag is reset serves as user designated sense condition input. Sense condition testing is effected by copying status register to accumulator.

SENSE B

Sense Input

User designated sense condition input. Sense condition testing is effected by copying status register to accumulator

SIN

Serial Input to E register

Under software control, data on this line are right shifted into E register by execution of SIO instruction

SOUT

Serial Output from E register

Under software control, data are right shifted onto this line from E register by execution of SIO instruction. Each data bit remains latched until execution of next SIO instruction.

FLAGS 0,1,2

Flag outputs

User designated general purpose flag outputs of status register. Under program control, flags can be set and reset by copying accumulator to status register.

AD00-AD11

Address bit 00 through Address bit 11

Twelve tri-state address output lines. SC/MP outputs 12 least significant address bits on this bus when NADS strobe is low. Address bits are then held valid until trailing edge of read (NRDS) or write (NWDS) strobes. After trailing edge of NRDS or NWDS strobe, bus is set to high impedance mode until next NADS strobe.

DB0

Address bit 12 (NADS Time)

Fourth most significant bit of 16 bit address

DB1

Address bit 13 (NADS Time)

Third most significant bit of 16 bit address

DB2

Address bit 14 (NADS Time)

Second most significant bit of 16 bit address

DB3

Address bit 15 (NADS Time)

Most significant bit of 16 bit address

DB4

R Flag (NADS Time)

When high, data input cycle is starting, when low, data output cycle is finishing.

DB5

I Flag (NADS Time)

When high, first byte of instruction is being fetched.

DB6

D Flag (NADS Time)

When high, indicates a delay cycle is starting ; that is, second byte of DLY instruction is being fetched.

DB7

H Flag (NADS Time)

When high, indicates a Halt instruction has been executed (In some system configurations, the H-flag output is latched and in conjunction with the CONTinue input, provides a programmed halt)

Note: The 8 bit bidirectional data bus is set to the high impedance (tristate) mode except when it is actually in use by SC/MP (NADS,NRDS or NWDS low). During the addressing interval of each input/output cycle (NADS low), SC/MP provides address and status outputs over the bus ; during the ensuing data transfer interval (NRDS or NWDS low) 8 bit input or output data bytes are routed over the bus.

drivers and receivers

Equivalent circuits for SC/MP drivers and receivers are shown below. All inputs have static charge protection circuits consisting of an RC filter and voltage clamp. These devices should still be handled with care, as the protection circuits can be destroyed by excessive static charge.

timing control

All necessary timing singles are provided by a three stage inverter ring oscillator contained on the SC/MP chip. Two control pins, XIN and XOUT permit the frequency of the oscillator to be controlled by any of the following methods:

  1. By leaving the XOUT pin unterminated and driving the XIN pin with an externally generated TTL clock. For this method, the frequency of the oscillator is equal to the frequency if the external clock input.
  2. By connecting a resistor-capacitor feedback network between the XIN and XOUT pins and GND
  3. By connecting a crystal with low pass filter network between XIN and XOUT and GND. For this method, the frequency of the oscillator is equal to the resonant frequency of the crystal and the low pass filter prevents unwanted harmonic oscillations.

In the discussions that follow, instruction execution and input/output timing are described in terms of microcycles. The time interval of a microcycle is four times the period of the oscillator.

instruction format

The SC/MP instruction repertoire includes both single and double byte instructions. A single byte instruction consists of an 8-bit operation code that specifies an operation that SC/MP can execute without further reference to memory> A double byte instruction consists  of an 8 bit operation code and an 8 bit data or displacement field. When the second byte represents a data field, the data are processed by SC/MP during execution of the instruction, thereby eliminating the need for further memory references. When the second byte represents a displacement value it is used to calculate a memory address that will be accessed (written into or read from) during execution of the instruction (refer to addressing).

data storage

SC/MP provides ten internal registers, seven of which are accessible to the programmer. The purpose and function of these registers are described below:

Program Counter - The program counter is a 16 bit register that contains the address of the instruction being executed. The contents of this register are automatically incremented by one just before each instruction is fetched form memory to enable sequential execution of the stored instructions. Under program control, the contents of this register also may be modified or exchanged with the contents of a pointer register to effect subroutine calls and program branches.

NOTE: The 16 bit address output of the program counter consists of a 4 bit high order address and a 12 bit low order address. When the program counter is incremented at the start of each instruction fetch cycle, only the 12 low order bits are affected; no carry is provided to the 4 high order bits. For systems employing memories of 4k or less, the high order bits can be ignored as they are set to 0000 following initialisation. For systems employing larger memories, the contents of a pointer register can be modified to select the desired 4k block of memory

Pointer Registers - the pointer registers are 16-bit general purpose registers that normally are loaded under program control with reference addresses that serve as page pointers, stack pointers and subroutine pointers. In applications having minimal memory addressing requirements, these registers may be used alternately as data storage registers.

NOTE: When interrupt requests are enabled, pointer register 3 is automatically referenced by the internal microprogram for formation of the starting address of the user generated interrupt service routine. In this case, the contents of pointer register 3 must be set

arithmetic and logic unit

not yet available

bus transfer logic

not yet available

status register

not yet available

control

not yet available

initialisation

not yet available

parallel data transfers

not yet available

bus utilization

not yet available

bus access

not yet available

input/output cycle

not yet available

input/output cycle extension

not yet available

serial data transfers

not yet available

interrupt

not yet available

microprocessor halt

not yet available

instruction set

not yet available

system implementation

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